A new truncation algorithm of low hardware cost multiplier

Multiplier is one of the most inevitable arithmetic circuit in digital signal design. Multipliers dissipate high power and occupy significant amount of the die area. In this paper, a low-error architecture design of the pre-truncated parallel multiplier is presented. The coefficients word length has been truncated to reduce the multiplier size. This truncation scaled down the gate count and shortened the critical paths of partial product array. The statistical errors of the designed multiplier are calculated for different pre-truncate values and compared. The multiplier is implemented using Stratix III, FPGA device. The post fitting report is presented in this paper, which shows a saving of 36.9 % in resources usage, and a reduction of 17 % in propagation time delay

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (s) are the highest when compared to other reported FCOTAs in the literature

Design LC oscillator for MF, HF& VHF using both ideal and practical operation amplifier

In general, the oscillator is a device that used in most circuits and system of electronics, electrical, and telecommunications. There are several kinds of oscillator contingent on frequency band use in a submission such as microwave, audio, and radio frequency. LC oscillator is one of the greatest mutual categories of oscillators, the applications of this oscillator was seemed to be increasing in modern devices, for actual high and very high frequencies to meet the speedy growth of progressive knowledge. That can be secondhand for radio frequency (RF), its productivity signal is frequently applied at the basis of radio communication classification in furthermost applications. In this paper, a designed Colpitts oscillator is covered from voltage amplifier with LC container. This strategy is done by two approaches. Primarily, is approved out exploitation hypothetical scheming. The subordinate is supported out exploitation imitation (Multisim 13). There are two proposal types of circuits the first for generate signal frequencies 0.5MHz,1MHZ,10MHz,20MHz,50MHz &100MHz, the second for generate signal frequencies 4.963MHZ, 5.031MHZ, and 5.756MHz respectively. The consequence is realized to be very hopeful